Fairchild Semiconductor

Overview

The F8 is actually a number of chips.

The 3850 CPU
The 3851 PSU (programmable Storage Unit)
- Read Only Memory
- Various additional logic functions
The 3852 DMI (Dynamic Memory Interface) for interfacing dynamic and static RAM
The 3853 SMI (Static Memory Interface)
The 3854 DMA (Direct Memory Access) combined with the 3852 implements Direct Memory Access logic
The 3856 and 3857 PSU 16 (16K Programmable Storage Unit) similar to 3851 but with more ROM.

The 3859 and 3870 devices will also be covered on this page. Those units are actually single chip microcomputers and would be an alternative to the F8 rather than a supporting unit. All of the devices require a +5V and +12V source. With a 2MHz clock, instruction execution times range from 1 to 6.5 machine cycles or 2 to 13 microseconds.

Here is a pin diagram of the 3850 CPU and 3851 PSU.

[image of F3850 pin diagram] [image of F3851 pin diagram]

The pin designation is as follows:

*3850 CPU Pin Assignment Description*
Pin Name	Description	Data Flow
DB0 - DB7	Data Bus Lines	Bidirectional
PHI, Write	Clock Lines	Output
I/O 00 - I/O 07	I/O Port Zero	Bidirectional
I/O 10 - I/O 17	I/O Port One	Bidirectional
ROMC0 - ROMC4	Control Lines	Output
EXT RES	External Reset	Input
INT REQ	Interrupt Request	Input
ICB	Interrupt Control Bit	Output
RC	Clock Oscillator	Input
XTLX	Crystal Clock Line	Output
XTLY	External Clock Line	Input
Vss, Vdd, Vgg	Power Lines

CPU Information

The 3850 CPU is consists of only the following:

The ALU
The control unit and instruction register
interface logic
Accumulator register

It has no memory addressing logic. Memory addressing regsters are supplied by one of the support chips. The Stack Pointer, Program Counter, and Data Counter are also maintained on the memory support chips. The F8 system is such that memory addressing logic will be duplicated if more than one memory device is in a system. There is a work around to solve the address contention problem. However, that subject will be covered later.

The two main advantages of not having memory address logic on the CPU:

Address lines (16 pins) are no longer needed on the system bus. These pins are re assigned as two 8-bit I/O ports.
Silicon real estate is no longer needed for memory addressing logic. The space is used for 64 bytes of RAM.

Register Information

This diagram shows the organization of the F8 system registers.

Note, there is one 8-bit Accumulator. The 64-byte scratchpad area can be thought of as 64 bytes of RAM, or as 64 8-bit secondary Accumulators. The instruction set allows the first 11 bytes to be accessed directly as secondary Accumulators. The other bytes can only be accessed using a type of implied addressing where the ISAR (Indirect Scratchpad Address Register) identifies the scratchpad RAM location. Since the 3850 does not have a Program Counter, Data Counter, or Stack Pointer, these registers are provided by the suport chips. The instruction set provides for register to register moves that move data between the scratchpad RAM and the Program Counter, Data Counter, or Stack Pointer. On the 3851 PSU, 3852 DMI, and the 3853 SMI devices, a 16-bit Data Counter (DC0), a 16-bit Data Counter Buffer (DC1), a 16-bit Program Counter (PC0), and a 16-bit Stack Pointer (PC1) are implemented.

DC0 is an implied addressing register.
DC1 is a buffer for DC0, the only instruction that can use this register is the one that swaps DC0 and DC1.
PC0 is a standard Program Counter.
PC1 the stack pointer is actually a buffer for the Program Counter. There are no push or pop instructions. jump to subroutine instructions save PC0 here.

If a stack is needed, it has to be implemented in software. The instruction set is relatively brief with 70 instructions. The opcode summary is also available here. Of course by today's (RISC) standards, that is still a lot.

Since address registers are present on every PSU, DMI or SMI device in an F8 system, these registers will be duplicated in any system that has more than a minimum amount of memory. As long as the sytem is correctly configured, this should present no problem.

Every memory device is connected to a common bus and therefore all memory is modified at the same time. For example, if there are two program counters in the system, each program counter would be updated at the same time.

Colophon

last modified 15MAR00

this home page is maintained by Lowell O. Turner.

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