Cosmac 1802

Introduction

The Cosmac 1802 is a one chip implementation of a previous two chip (CDP1801 and CDP18101) set produced by RCA. A major advantage over it's competitors was it's CMOS fabrication. Another advantage was it's support for DMA transfers. Perhaps the most famous use of the Cosmac was in the "Elf." This "personal computer" was introduced as a build it yourself series in the magazine Popular Elctronics in August of 1976. There is even an Elf emulator for windows written by Bill Richman and Chris Radek in Sep 1997. It can be found at this location. I do have an alternative site with instruction set cards for this chip and a few others. The site is in the UK at http://www.comlab.ox.ac.uk/archive/cards.html. Apparently, Harris Semiconductor still produces this chip and has complete documentation.

General Description

The 1802 can operate at a maximum clock frequency of 6.4 MHz using a +10V power supply. The device does have an on-chip clock generator. The chip uses a multiplexed address bus which increases circuit complexity by requiring a latch to hold the high order byte.

Register Description

As noted on the image below,

The D register is the primary accumulator
The R registers (16 of them) can function as:
- Program Counter
- Data Counter
- General purpose registers
The P register points to the R register acting as the Program Counter
The X register points to the R register acting as the Data Counter.
The T register holds X and P following an interrupt.

The first three registers have dedicated functions

R0 is the Address pointer used by the DMA logic
R1 points to a valid interrupt service routine
R2 is a primitive stack pointer

Addressing Modes

The 1802 allows implied addressing of data memory. This means that all access to data must be indexed by a general register. This is done by either specifying the register in the op code, or using an instruction that makes the X register identify the correct R register. The 1802's program memory is directly addressed. The flexibility of the address control lines allow program and data memory to exist in a shared address space. Branch instructions are two and three bytes long. The two byte instruction uses paged, direct addressing. The second byte replaces the low order byte of the program counter. This allows for jumps within a 256 byte "page."

Flags

The 1802 does not have a status register. However, it does have seven flags that can provide status information.

Data Flag is equivalent to a carry status
Interrupt Enable Flag set to one to enable interrupts
following are direct logic control statuses
- Four I/O Flags (EF1 - EF4) these are inputs corresponding to chip pins.
- Q status can be read or written and corresponds to a chip pin.

I/O

The 1802's I/O i limited to the EF and Q flags described above. Other I/O peripherals would be memory mapped (as opposed to port mapped.)

Interrupt processing

External logic can assert an interrupt at any time by pulling INT low. When this happens, the CPU will do the following:

The P and X registers are copied to T.
The P and X registers are loaded with the numbers 1 and 2 respectively.
interrupts are disabled.

As the above list notes, the interrupt service routine begins at the location pointed to by R1. Any data accessed by the ISR must be pointed to by R2. If nested interrupts are going to occur, The programmer will have to keep track of all return addresses except the most recent. Only by testing the four input signals (EF1 - EF4) can multiple interrupt sources be differentiated. As a result, in a multiple interrupt source scenario, the ISR will need a series of branch on condition instructions to route the program to the proper service routine.

DMA

From a programming standpoint, DMA is extremely simple. R0 is loaded with the transfer address, external logic then takes over by asserting DMA-IN* or DMA-OUT*. The asterisk indicates an active low signal.

Pin Diagram

Instruction Information

The following links to table 1 and table 2 summarize the 1802 instruction set. (incomplete) Of note is the fact that register to register data transfers occur via the D register. Since all data transfers between the CPU and external logic are alo via the D register, bottlenecks can occur. This would be the case if it is not possible to simply change the contents of X instead of moving data between registers.

Colophon

last modified 26OCT04

this home page is maintained by Lowell O. Turner.

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Disclaimer: This document in no way represents Nyx. All opinions and errors are mine alone.

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